ATM Throughput & Overhead
ATM, as with every protocol - has overhead. Overhead is control and synchronization bits. For every 53-byte ATM cell, there is a control field of 5 bytes (6 bytes with CBR ATM). Therefore the cells have a throughput of 48 bytes for VBR, and 47 bytes for CBR. With VBR, the protocol requires some additional available BW above the SCR (Sustained Cell Rate), and therefore, SCR cannot be equal to PCR (Peak Cell Rate).
Port Information Rate (PIR)
PIR = Port Speed - line overhead - cell tax
Where: line overhead = SONET overhead
Cell Tax = ATM header (5 bytes out of 53 per cell)
NOTE: when the customer orders a specific data rate for a PVC, we charge them and supply them with that actual data throughput, and The provider supplies the overhead. That way, the customers do not pay for the SONET overhead, nor do they pay for the cell tax.
Throughput
The following shows how overhead and throughput is calculated for an ATM DS1.

*** these data rates differ slightly from the ATM Product Guide, but use these since the info is newer
|
Access Type |
Maximum VBR SCR (64 Kbps and 1 Mbps increments) |
Maximum VBR PCR (Line Rate) |
|
DS1 |
973 Kbps |
1.390 Mbps |
To calculate the maximum SCR that a customer can be configured with for VBR (Variable Bit-Rate)- find the Maximum PCR rate in the Table below, and multiply that rate by 0.7
To calculate the maximum PCR that a customer can be configured with for CBR (Constant Bit-Rate) - find the Maximum PCR rate in the Table below. Note that CBR has no SCR - only PCR. Some say that with CBR, SCR=PCR since it is a "Constant" Bit Rate.
NOTE: a customer that orders an OC12 (622 Mbps) only gets less than half that – The provider throttles the data rate down (PCR = 271 Mbps) so that no single OC12 customer can cause congestion problems on the network.
|
Access Type |
PVC Type Supported |
Port Transfer Rate (Mbps) |
ATM Cells per second |
Information Rate Increments (in Kbps or Mbps) |
Maximum PCR / Info Rate (Mbps)[1] |
Info Rate (Mbps) |
|||||
|
|
|
|
|
56 K |
64 K |
1 M |
1.5 M |
1.544 M |
CBR |
VBR-nrt |
UBR |
|
DS1 |
VP/VC |
1.536 |
3,602 |
|
X[2] |
X |
|
|
1.286[3] |
1.383[4] |
1.383 |
|
2xDS1 |
VP/VC |
3.046 |
7,165 |
|
X |
X |
|
|
2.559 |
2.751 |
2.751 |
|
3xDS1 |
VP/VC |
4.569 |
10,757 |
|
X |
X |
|
|
3.842 |
4.130 |
4.130 |
|
4xDS1 |
VP/VC |
6.093 |
14,350 |
|
X |
X |
|
|
5.125 |
5.510 |
5.510 |
|
5xDS1 |
VP/VC |
7.616 |
17,942 |
|
X |
X |
|
|
6.408 |
6.889 |
6.889 |
|
6xDS1 |
VP/VC |
9.139 |
21,535 |
|
X |
X |
|
|
7.692 |
8.269 |
8.269 |
|
7xDS1 |
VP/VC |
10.662 |
25,128 |
|
X |
X |
|
|
8.975 |
9.649 |
9.649 |
|
8xDS1 |
VP/VC |
12.186 |
28,720 |
|
X |
X |
|
|
10.258 |
11.028 |
11.028 |
|
DS3 |
VP/VC |
40.704 |
95,980 |
|
X |
X |
|
|
34.284 |
36.856 |
36.856 |
|
OC3c |
VP/VC |
149.760 |
353,187 |
|
X |
X |
|
|
126.158 |
135.623 |
135.623 |
|
OC12c |
VP/VC |
599.040 |
1,412,810 |
|
X |
X |
|
|
126.158[5] |
271.259 |
271.259 |
|
DS1 Circuit Emulation |
VC |
|
|
|
|
|
|
X |
1.544 |
N/A |
N/A |
|
ATM/FR Service Interworking |
VC |
|
|
X |
X |
|
|
|
N/A |
1.390 |
N/A |
|
ATM/IP Gateway |
VC |
|
|
|
X[6] |
|
X |
|
N/A |
12 |
N/A |
PLCP Throughput
HEC Throughout
Customers now have the option of HEC mapping, which has 8% less overhead. If your customer will be using HEC mapping, take the value in the Maximum PCR column and:
HEC mapping Max Throughput = PCLP Max Throughput x 1.086
DS3 has 672 DSo's
You would think that DS3 port speed = 672 x 64k = 43.008 Mbps
However, there is overhead (very complex, and difficult to find anything explaining the DS3 overhead) . . . therefore :
DS3 = 44.736 Mbps
PLCP mapping takes up 10% of the bandwidth, so you only get approximately 40.26 Mbps of available bandwith. Then :
Max CBR rate = .95 x port speed = .95 x 40.26 = 38.2 Mbps
taking into account the framing bits (1 out of every 193 bits) . . .
(1/193) x 38.2 Mbps = .41 Mbps
CBR Payload (using AAL1, 47 bytes per cell) = [(47/53) x 38.2 Mbps] - framing overhead
= 33.87 Mbps - .41 Mbps = 33.46 Mbps
NOTE1: the ATM product guide says 34 Mbps (close enough)
Our DS3 Throughput just Increased by 8% - DS3 HEC Mapping
Direct or HEC mapping is currently available on any of the ATM switch platforms for DS3 circuits. For orders requiring HEC mapping please indicate the request in the comments section of the order and place a call into the BSC to provide a red-flag on an upcoming order. The benefit of HEC mapping is only truly recognized at line rate—as a slight increase of cells (8%)+ can be sent into the network within the CDVT.
So now we can offer a PCR of 40 MB on DS3's, in stead of 34 Mbps !!
The new Marconi ASX-4000 edge switches support “HEC” or "Direct" mapping which has less overhead than PLCP.
there is a small amount of overhead associated with IMA (Inverse Multiplexed ATM, for NxT1). The overhead is negligible, but it is there. I am including a table of PCR values for IMA connections. To calculate the SCR, just multiply PCR by .7
It is true that the actual line rates are multiples for the T1 bit rate of 1.544 Mbps. For example, the 2 x T1 port has an interface rate (bit rate) of 3.088 Mbps (2 x 1.544 Mbps). However, the ATM "Information Rate", for NxT1, is based upon multiples of the 1.523 Mbps transfer rate per T1 instead of 1.536 Mbps. Therefore the rate would be 3.046 Mbps (2 x 1.523). That is the actual amount of ATM cells being transferred - then you would need to account for line signalling and ATM 5-byte overhead to get the actual PCR.