The SONET Model

***Level 3 uses “span” (same as Line) and “segment” (same as Section)

The Equipment at the Endpoints

(SONET Transmit and Receive Boxes)

SONET transmitter - a Layer 1 device - it takes data from Layer 2 and “Frames it into SONET frames” at Layer 1.

SONET receiver  - also a Layer 1 device - it takes SONET frames from the “Layer 0” medium (the fiber), strips off the headers, and hands the payload (which are called frames for FR, Cells for ATM, etc) up to the Layer 2 (Data Link) processing hardware/software.

Example - the Xelic STS-3/STM-1 Framer Chip

This is an ASIC (Applications Specific Integrated Chip) that they call a “Network Core”.  A router or switch could use one of these to prepare frames for transmission and to receive frames.

Transmitter and Receiver - full duplex operation combines transmit and receive functions with configurations for bypass, streaming, and mapping modes of operation at a data rate of 155Mb/s.

• Transmitter  - the XCS3 transmitter performs B1/B2/B3 parity calculations and insertions, scrambling, and the insertion of transport and path overhead from an external overhead port or through internal register programming.
   

• Receiver - the XCS3 receiver byte aligns incoming data, de-scrambles appropriate frame byte locations, performs pointer processing for contiguous concatenated payloads, detects error conditions, accumulates various condition counts, and extracts transport and path overhead information to both internal register locations and external overhead ports.

Monitoring - a standard processor interface is provided for internal register configuration and the reporting of status, interrupt, and performance monitoring information.

Testing - various test modes are available for diagnostic purposes to transport fixed value payload information, force selected error conditions, and corrupt data to verify various interpreter algorithms and error counter operations.

Features

• Complies with GR-253-CORE, ITU-T G.707, G.783, and ANSI T1.105 standards

• Flexible core architecture includes variable size data bus widths of 8 to 32 bits

• Supports transmit and receive facility and terminal loopback configurations

• Accepts streaming SONET/SDH frames or mapped client signals for transport

• Flexible insertion and extraction of transport and path overhead byte information

• Programmable general purpose registers available for the insertion and extraction of any frame transport or path overhead location

• Data corruption available through internal register programming for debug or test purposes

• Performs SONET/SDH frame alignment with LOS and LOA detection

• Programmable detection of LOF and OOF error conditions

• Generates line AIS SONET/SDH frames for LOS and/or LOF error conditions

• Supports scrambling/descrambling (1+x⁶+x⁷) with polynomial corruption capability for diagnostics

• Programmable counters for user defined interval or errored second accumulation

• Detects and accumulates B1/B2/B3 parity, path REI, and line REI error conditions in configurable bit or block error counters

• Detects APS conditions (including line AIS and line RDI) and implements programmable acceptance count criteria

• Provides insertion and extraction of section trace (J0) messages for 16 or 64 byte lengths and optional legacy J0/Z0 support

• Provides insertion and extraction of path trace (J1) messaging

• Detects path RDI and path REI error conditions

• Detects LOP, Path AIS, and concatenation error conditions

• Internal counters to track pointer increments and decrements

• Generates frame start, SPE valid, SPE start, and transport/path overhead port control signals