T3 and the DS3

This section is extremely complex, and has been laid out with very exacting details. It is very dry reading - but stick with it. Once you truly understand the DS3 - you will then begin to grasp many other concepts of telephone, since the DS3 concepts are applied to many other data communication technologies.

Before you can understand the DS3 signal, you must know the hardware components and some of the protocols and standards associated with the components of the DS3 . . . the DS1 and the DS2. For this section, since the DS0 and DS1 have already been described in detail, we can skip the DS0 level. However, we will continue to discuss the DS1, since it is a direct contributor to the DS2 and DS3.

M13 Asynchronous - this is the original standard DS3, which will be used for the majority of this page. The C-bit Parity will be described after, and it can be described quickly, since it makes a simple change. The M13 Asynchronous DS3 is formed using a 2-stage process, where stuff bits are added to both the DS1-to-DS2 stage, and also the DS2-to-DS3 stage. Since this does not provide end-to-end parity checks, it has been largely replaced by the more efficient C-bit parity DS3 structure

C-bit Parity - it became apparent that once stuff bits were added during this DS1-to-DS2 stage, the signals were synchronized, and the adding of stuff bits during the DS2-to-DS3 stage was redundant and unnecessary. However, since "C-bits" were already reserved for the control of the stuff bits during the 2nd stage - the C-bit parity structure reassigns them for other purposes, such as alarms, parity, and error control. Therefore, this format makes use of bits that were previously used in a useless fashion, and as a result, the T3 is more stable and efficient. Most providers use C-bit Parity for their DS3 services.

The de-facto DS3 data rate is given as 44.736 Mbps in many sources, but they never explain how to get there. It is common knowledge that an M1/3 (Multiplexer DS1 to DS3) is used to combine T1 signals onto a single T3 using TDM (Time Division Multiplexing). In actuality, the data rate was chosen because it is an even multiple of the sampling rate (8 kbps) and it is large enough to allow for more than enough stuff bits, which are required for the timing drift in the T1's.

At the provider's POP, the M 1/3 is typically part of a larger, more complex unit called a DCS (Digital Cross-Connect System). The DCS is also called DACS (Digital Access and Cross-Connect System). In the old days, the POP would use a multiplexer to combine the T1 signals, and a large physical patch panel with cords and plugs to route the DS1's and map them to different DS3's. In this way, a T1 private line could come into the POP riding on one DS3, be broken out by an inverse MUX (M 3/1), sent through the patch panel, and onto another input line to another Mux (M 1/3) which would combine it with other T1's onto another DS3 and it would then continue it's path across the country.

The DCS replaced the old, clumsy, time-consuming patch panel with digital circuitry which could be instantly configured and mapped from a terminal. There are many brands, and types of DCS units. In the early days, the DCS and MUX were two separate units, but have been combined, so that most DCS units have multiplexing capabilities built-in. Most of them actually consists of multiple M1/0's and M 1/3's and digital "patch panels" (cross-connects) - many are expandable and allow add-on units. The DCS has the capability of mapping either DS0's from one DS1 to the next - or DS1's from one DS3 to the next.

*** For the purposes of this discussion . . . the creation of a DS3 from DS1 signals . . . only multiplexing is required - no cross connects. Therefore we will only address the Multiplexer in this discussion from here on . . ..

We have all seen network diagrams which depict 28 T1's terminating to a multiplexer, with one T3 coming out the other end.

Internal Processes - the diagram itself is actually correct, but there is some serious processing going on inside the mux, which must be examined in order to understand the composition of the T3. The diagram can actually lead the reader to the fallacy that the conversion is a direct aggregation of T1's to T3. But the process requires an intermediate conversion to multiple T2's as described below.

Overhead - from what we see . . . the fact is, that one DS3 has 28 x 24 = 672 DS0's, each at 64 kbps - we see that the payload speed, or throughput, is 672 x 64k = 43.008 Mbps. Since the data rate of a T3 is already established at 44.736 Mbps, the rest is overhead, where Overhead = 44.736 - 43.008 = 1.728 Mbps (or 1728 kbps). There is overhead, but the model is wrong, as will be explained shortly.

Even if we consider that a T1 has 8 kbps overhead for the framing bits (one out of every 193 bits), then the overhead would be 28 x 8 kbps = 224 kbps. This is way less than the actual overheard that we just calculated at 1728 kbps. From what we see - it is unclear where all this additional overhead is coming from.

It's in the Stuff Bits - T3's have been designed to take care of the drift in T1's by adding reserved space for stuff bits. In fact, even if the T1's are tightly synched - the stuff bits are still there - they just aren't used and are discarded at the terminating MUX that strips the T1's back out from the T3. Think of it as an airline that undebooks passengers, so they always have room to spare. Recall that T1's are actually "pleiosynchrnous" - "almost synchronous" and require stuff bits at the mid-span meet (wherever two T1 systems with 2 different clock sources meet). T3's have much more stringent timing constraints that T1's, because the T1's drift - and they must deal with the process of inserting stuff bits, and the even more difficult process of signaling the presence of stuff bits, where the stuff bits are, etc..

There are two steps in the creation of a DS3 signal . . . DS1 to DS2, then DS2 to DS3. The creation of a DS3 signal is actually a very complex, two-stage process, which involves the DS2 data stream. The DS2 is not a commercial product. It is not available for customers, but it is an intrinsic component of the DS3, and does exist within the M 1/3 multiplexer.

Note that the M 1/3 DCS is a combination Multiplexer and cross-connect (a digital "patch panel"). It has the capability of mapping DS0's from one DS1 to the next, but for the purposes of this discussion - only the multiplexing stage is required.

Now, does this come out to 44.736 Mbps if we multiply? No - because there are DS3 control bits, not associated with the 8 kbps of each T1, and there are also stuff bits inserted by each DS1/2 Mux, since T1's are plesiosynchronous.

Plesiosynchronous - signals that are at almost an identical rate, but the timing source can differ by a very small amount. These signals can be aligned by inserting dummy bits into the stream, known as "stuff bits". Again, T1's are plesiosynchronous - not synchronous !!

Bit Interleaving - the building blocks of the T3 employ TDM, as does the T1 structure. However, the signals at both stages employ "bit interleaving", and this means that the sub-frames contain bits from all the inputs, in the order shown:

Stage 1 is the creation of seven DS2 streams of data - each comprised of four T1's and overhead..

The DS2 data rate is established at 6.312 Mbps (they picked a value that is evenly divisible by the sampling rate of 8 kbps and that includes plenty of extra bits which can be used for stuff bits)

Unlike the well-known B8ZS, DS2 signals use B6ZS (BiPolar with Six Zero Substitution) instead of B8ZS, which was used with DS-1 signals. It is more stringent in that it only allows a maximum of 5 consecutive zeros to occur. If six zeros occur, they are replaced with special bipolar violation code word of either 0+-0-+ (if polarity of preceding pulse was +) or 0-+0+- (if polarity of preceding pulse was -).

However, 4 x 1.544 = 6.176 Mbps, not 6.312 Mbps, so this leaves 136 kbps of overhead. The overhead occurs both as the first bit in each DS2 49-bit block (OH bits) and as the first bit or bits after the OH bit (stuff bits). The two types of overhead can be described as follows :

Stuff Bits (also called "Pulse Stuffing") and the "Timing Window" - at each T1-to-T2 mux, there are 4 incoming T1's. The incoming T1's, by the accepted standards, can have a specific allowable bit drift of 200 bps for each T1 in either direction - this is the "timing window". Since a T1 is at 1,544,000 bps, the 200 bps allows a drift of only about 0.1% Nevertheless, the drift must be corrected by adding stuff bits where appropriate. This is actually a very difficult process, and the majority of the 136 bits of overhead are assigned to this task. The insertion of stuff bits is simple, but the management is difficult (signaling the presence of stuff bits, the number of stuff bits, the location of the stuff bits are, etc.) If there are any stuff bits in a block, they always appear at the beginning of each block, just after the Control bit. After that comes the data.

Stuff Control Bits are used to identify the contents of Stuff Bits. If a majority of the Stuff Control Bits are a 1, the Stuff Bit is holding an inserted bit. Otherwise, the Stuff Bit contains data. Each subframe has three Stuff Control Bits (Ci) and one Stuff Bit (Si). Since the Stuff Bit may or may not contain data, each subframe may contain either 288 or 287 data bits.

Each Master Frame is divided into four Master sub-frames, and each sub-frame has six "Blocks". The four T1's are bit-interleaved into these blocks, each block contains bits from each T1. The following is one block of the DS2 data stream - no stuff bits are shown, but they are inserted whenever one of the T1's data streams drifts more than 200 bps ahead of the others. The manner in which this is proprietary and varies from one vendor to the next, but the standard must be adhered to.

NOTE: although a stuff bit is shown here - the vast majority of blocks contain no stuff bits

Each of these subframes has 6 blocks of 49 bits. One bit is overhead - the one bit is reserved for alignment, alarms, and as a flag to specify whether or not stuff bits were added. The other 48 bits are data and stuff bits. The following diagram shows a block (top third of image) with 2 stuff bits in blue. They are shown as an example, but the majority of blocks have no stuff bits, or one at the most. The clock sources are very close, and only an occasional stuff bit is needed, typically.

Note that there are six blocks in each subframe. The first bit of each block is an OH bit, and they cycle through as M-bits, F-bits, and C-bits as follows :

F-bits - Framing bits - there are 8 F-bits per frame . . . 2 per subframe. For each subframe, they occur at the beginning of Block 3 and the beginning of Block 6 and have a simple pattern of 0,1 which repeats. They are used to align the frames within the signal. This is related to synchronization, but instead of telling the receiving end how to run the clocking (which all the bits do this) - the F bits tell the receiving end where the Frames start. Note that not every frame has a framing bit

M-bits - Multiframing bits - there are 4 M-bits per frame . . . 1 per subframe. For each subframe, they occur at the beginning of Block 1 pattern of 0,1,1,X where X can be a zero or a 1.

C-bits - Control bits for stuff bits - there are 12 C-bits per frame . . . 3 C-bits per subframe. They occur at the beginning of Blocks 2, 4, and 5 of each subframe. For each subframe, if all 3 C-bits are 1's - then one stuff bit is present in the first OH bit in the following subframe. If all 3 C-bits are zero, then there is no stuff bit, and the reserved bit should be treated as a normal data bit. Three C bits are used to protect against a bit-error. If one C-bit differs from the other two, it is disregarded and all three are assumed to be the same.

In order to truly understand what is going on - it helps do go through the math - just once. The final DS2 is comprised of Data, OH bits, and Stuff bits. We can look at it as having 4 inflated T1 data streams . . . inflated by the stuff bits. The reserved stuff bits are there regardless of whether or not they are needed. They may, or may not be occupied by actual stuff bits. The OH bits tell the system whether or not they are.

Overhead Ratio (from one frame) = 24 OH bits per 1176 bit frame = 24/1176 = 2.04%

DS2 data rate is established at 6.312 Mbps = 6,312 kbps = 6312000 bps (evenly divisible by sampling rate of 8 kbps)

Since there are 4 subframes, each subframe has an OH data rate of 128816/4 = 32204 bps

Taking the standard DS2 data rate, we subtract the OH bits to see what is left for data and stuff bits :

This represents an intermediate four data components that take each original T1 input of 1544000 and add bits that are reserved for stuff bits - the new data rate for this intermediate "T1 with stuff bits" is :

Circling back - the data rate of the DS2 can now be found by combining the four intermediate, inflated T1 streams (which include the bits reserved for stuff bit s) with the OH bits.

The following Pie chart depicts the components of the DS2. As the four T1's timing drifts, the small blue slice will move with time, as the need for stuff bits varies with time. Since the actual percentages for OH and stuff bits is so small, the slices are artificially enlarged so that they can be seen.

Thankfully - we can make this section much shorter. We covered the laborious details in Stage 1, which is almost an exact re-enactment of Stage 2. The only difference is in the numbers :

Stage	Bits per Block	Blocks per SubFrame	SubFrames per Frame	Bits per Frame
Stage 1	49	294	4	1176
Stage 2	85	8	7	4760

7 x 6.312 = 44.184 Mbps (not the established 44.736 Mbps - this means there is 552 kbps of overhead added by this stage of processing). The extra bits, similar to the DS2 rate, are used for

Stuff Bits - at the T2-to-T3 mux, there are 7 incoming T2's. Just as the first stage did - the drift must be corrected by adding stuff bits where appropriate. However, any drift of the T1's has already been largely handled by the first stage stuff bits, so there will be very few, if any, stuff bits inserted during this stage.

The DS3 Frame - each frame is divided into seven subframes, and each subframe has eight "Blocks" of data - which are 85 bits apiece. Like the DS2, the seven T1's are bit-interleaved into these blocks, and each block contains bits from each T1. Again, the first bit is a control bit, and stuff bits are added, if needed, directly after the control bits. Like the DS2, the stuff bits are placed within the payload - which for DS3 blocks is 84 bits.

Again, the first bit is a control bit, and stuff bits are added, if needed, directly after the control bits. Like the DS2, the stuff bits are placed within the payload - which for DS3 blocks is 84 bits.

Overhead of Stage 2 = 56 bits per 4760 bit frame - the overhead ratio = 56/4760 = 1.17%

Overhead from Control bits = overhead ratio x 44736 = 526.3 kbps (assuming stuff bits are approx zero)

Recall that at the top of this page, we discussed the two forms of DS3's - here are the two types of blocks. Note that the modern C-bit parity replaces the C-bits with useful control bits (the C-bits for bit-stuffing are redundant, since the first stage of creting the DS2 stage took care of stuff bit already). DO NOT CONFUSE THESE BLOCKS WITH THE DS2 BLOCKS DISCUSSED EARLIER !! The DS2 blocks do have the F, M, and C-bits, but they do not have the X or P bits of the DS3.

	85 BITS (8 blocks)
1	X	F1	C₁	F0	C₂	F0	C₃	F1
2	X	F1	C₄	F0	C₅	F0	C₆	F1
3	P	F1	C₇	F0	C₈	F0	C₉	F1
4	P	F1	C₁₀	F0	C₁₁	F0	C₁₂	F1
5	M0	F1	C₁₃	F0	C₁₄	F0	C₁₅	F1
6	M1	F1	C₁₆	F0	C₁₇	F0	C₁₈	F1
7	M0	F1	C₁₉	F0	C₂₀	F0	C₂₁	F1

	85 BITS (8 blocks)
1	X	F1	AIC	F0	C2	F0	FEAC	F1
2	X	F1	DL	F0	DL	F0	DL	F1
3	P	F1	CP	F0	CP	F0	CP	F1
4	P	F1	FE	F0	FE	F0	FE	F1
5	M0	F1	DL	F0	DL	F0	DL	F1
6	M1	F1	DL	F0	DL	F0	DL	F1
7	M0	F1	DL	F0	DL	F0	DL	F1

Control Bit	Comment
X, X	They can equal 0 or 1, but they must be the same.
F1 F0	Frame bits. They always appear in a 1 0 0 1 sequence.
AIC = C1	Application identification channel. There must be one of these in every M-Frame.
FEAC = C3	Far-end alarm and control channel
DL = C4 - C6 C13 - C15 C19 - C21	Data link. This is terminal to terminal path maintenance.
P	Parity bit. This is checked and corrected by all terminal equipment. They can equal 0 or 1, but they must be the same.
CP	Control parity. This bit goes unchanged through the system from end to end. It is constantly compared, and if it is not the same, an error condition exists.
FEBE/FE	Far end block error
M0, M1	Multiframe alignment signal

Frame Alignment Signal - The frame alignment signal (F1, F0) identifies the subframe and, accordingly, all the control-bit time slots. The multiframe alignment signal (M0, M1, M0) locates the M-Frame.

X-Bits - The X-bits at the beginning of subframes 1 and 2 must be identical, either 00 or 11, in any given M-Frame. DTE can use the X-bits for asynchronous, low-speed signaling, but the X-bit states cannot be changed more than once per second. The reason is that network transmission equipment uses rates faster than one per second for control purposes.

P-Bits - These are parity bits (beginning of subframes 3 and 4). DS3 transmitters count parity in all 4704 information time slots after the first X-bit in an M-Frame. The parity information is then inserted in the P-bit positions of the next M-Frame. P-bits are checked while the signal goes through, and any errors are corrected to prevent downstream alarms.

C-Bits - There are 21 C-bits (C1-C21), seven of which are defined.The other 14 are not used and are set to 1.

Application Identification Channel - This bit (C1) in subframe 1 has to be set to 1 in the C-bit parity format so that C1 can be used as a frame-format identification bit in subsequent DS3 terminal and monitoring equipment.

Control Parity Bits - The transmission equipment sets these bits in subframe 3 to the value of the P-bits. The receiving equipment determines if there is an error condition by computing the parity based on M-Frame n with the parity received in the CP bits in M-Frame n+1.

Far End Block Error - The FE (FEBE) bits are in subframe 4. The receiving equipment indicates the existence of a parity error by setting the FE bits to 0. If there is no parity error event, it sets the FE bits to 1. This arrangement allows the end-to-end performance to be determined by monitoring the FE bits at any point on the DS3 path in the opposite direction of transmission. The P-bits cannot monitor the DS3 path since they are corrected by each facility in the DS3 path. If the far-end terminal detects an out-of-frame (OOF) condition, it transmits that information to the near-end terminal by setting the X bits in the outgoing direction to zero for one second.